ECOSCALE
Energy-efficient Heterogeneous COmputing at exaSCALE
- Funded by: European Commission
- Project Acronym: ECOSCALE
- Funded under: Horizon 2020 (H2020-EU.1.2.2.)
- Budget: 688 625.01 € (Overall: 4 237 397,50 €)
- Start Date: 1st October 2015
- Duration: 46 months
- Website(s): CORDIS
More Info
In order to sustain the ever-increasing demand of storing, transferring and mainly processing data, HPC servers need to improve their capabilities. Scaling in number of cores alone is not a feasible solution any more due to the increasing utility costs and power consumption limitations. While current HPC systems can offer petaflop performance, their architecture limits their capabilities in terms of scalability and energy consumption. Extrapolating from the top HPC systems, such as China’s Tianhe-2 Supercomputer, we would require an enormous 1GW power to sustain exaflop performance while a similar yet smaller number is triggered even if we take the best system of the Green 500 list as an initial reference.
Apart from improving transistor and integration technology, what is needed is to refine the HPC application development and the HPC architecture design. Towards this end, ECOSCALE will analyse the characteristics and trends of current and future applications in order to provide a hybrid MPI+OpenCL programming environment, a hierarchical architecture, runtime system and middleware, and a shared distributed reconfigurable hardware based acceleration.
Publications
Peer reviews Articles
- Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level SynthesisAuthor(s): Liang Ma, Luciano Lavagno, Mihai Teodor Lazarescu, Arslan Arif
Published in: IEEE Access, Issue 5, 2017, Page(s) 18953-18974, ISSN 2169-3536
DOI: 10.1109/ACCESS.2017.2750923 - Efficient FPGA Implementation of OpenCL High-Performance Computing Applications via High-Level SynthesisAuthor(s): Fahad Bin Muslim, Liang Ma, Mehdi Roozmeh, Luciano Lavagno
Published in: IEEE Access, Issue 5, 2017, Page(s) 2747-2762, ISSN 2169-3536
DOI: 10.1109/ACCESS.2017.2671881 - Performance and energy-efficient implementation of a smart city application on FPGAsAuthor(s): Arslan Arif, Felipe A. Barrigon, Francesco Gregoretti, Javed Iqbal, Luciano Lavagno, Mihai Teodor Lazarescu, Liang Ma, Manuel Palomino, Javier L. L. Segura
Published in: Journal of Real-Time Image Processing, 2018, ISSN 1861-8200
DOI: 10.1007/s11554-018-0792-x - DDRNoCAuthor(s): Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis
Published in: ACM Transactions on Architecture and Code Optimization, Issue 15/2, 2018, Page(s) 1-24, ISSN 1544-3566
DOI: 10.1145/3200201 - Decoupled Fused CacheAuthor(s): Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
Published in: ACM Transactions on Architecture and Code Optimization, Issue 15/4, 2019, Page(s) 1-23, ISSN 1544-3566
DOI: 10.1145/3293447
Conference proceedings
- A Scalable Runtime for the ECOSCALE Heterogeneous Exascale Hardware PlatformAuthor(s): Paul Harvey, Konstantin Bakanov, Ivor Spence, Dimitrios S. Nikolopoulos
Published in: Proceedings of the 6th International Workshop on Runtime and Operating Systems for Supercomputers – ROSS ’16, 2016, Page(s) 1-8
DOI: 10.1145/2931088.2931090 - ECOSCALE: Reconfigurable Computing and Runtime System for Future Exascale SystemsAuthor(s): Mavroidis, Iakovos; Papaefstathiou, Ioannis; Lavagno, Luciano; Nikolopoulos, Dimitrios; Koch, Dirk; Goodacre, John; Sourdis, Ioannis; Papaefstathiou, Vassilis; Coppola, Marcello; Palomino, Manuel
Published in: Design, Automation & Test in Europe (DATE) 2016, 2016
DOI: 10.5281/zenodo.34893 - Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCLAuthor(s): Fahad Muslim, Alexandros Demian, Liang Ma, Luciano Lavagno, Affaq Qamar
Published in: Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, 2016, Page(s) 141-145
DOI: 10.15439/2016F327 - Implementation of a performance optimized database join operation on FPGA-GPU platforms using OpenCLAuthor(s): Mehdi Roozmeh, Luciano Lavagno
Published in: 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2017, Page(s) 1-6
DOI: 10.1109/NORCHIP.2017.8124981 - High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and SynthesisAuthor(s): Liang Ma, Fahad Bin Muslim, Luciano Lavagno
Published in: 2016 European Modelling Symposium (EMS), 2016, Page(s) 157-162
DOI: 10.1109/EMS.2016.036 - Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA PlatformsAuthor(s): Junnan Shan, Mario R. Casu, Jordi Cortadella, Luciano Lavagno, Mihai T. Lazarescu
Published in: Proceedings of the 56th Annual Design Automation Conference 2019 on – DAC ’19, 2019, Page(s) 1-6
DOI: 10.1145/3316781.3317821 - FusionCache: Using LLC tags for DRAM cacheAuthor(s): Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
Published in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Page(s) 593-596
DOI: 10.23919/date.2018.8342077 - A Survey on FPGA VirtualizationAuthor(s): Anuj Vaishnav, Khoa Dang Pham and Dirk Koch
Published in: 28th International Conference on Field Programmable Logic and Application (FPL), 2018 - Resource Elastic Virtualization for FPGAs Using OpenCLAuthor(s): Anuj Vaishnav, Khoa Dang Pham, Dirk Koch, James Garside
Published in: 2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018, Page(s) 111-1117
DOI: 10.1109/fpl.2018.00028 - ZUCL: A ZYNQ UltraScale+ Framework for OpenCL HLS ApplicationsAuthor(s): Khoa Pham, Anuj Vaishnav, Malte Vesper, Dirk Koch
Published in: FSP Workshop 2018; Fifth International Workshop on FPGAs for Software Programmers, Issue 31-31 Aug. 2018, 2018 - Live Migration for OpenCL FPGA AcceleratorsAuthor(s): Anuj Vaishnav, Khoa Pham, Dirk Koch
Published in: 2018 International Conference on Field-Programmable Technology (FPT), 2018, Page(s) 38-45
DOI: 10.1109/fpt.2018.00017 - IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAsAuthor(s): Khoa Pham, Edson Horta, Dirk Koch, Anuj Vaishnav, Thomas Kuhn
Published in: 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2018, Page(s) 36-43
DOI: 10.1109/mcsoc2018.2018.00018 - FreewayNoC: A DDR NoC with Pipeline BypassingAuthor(s): Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis
Published in: 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018, Page(s) 1-8
DOI: 10.1109/nocs.2018.8512160 - EFCAD — An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-CompilationAuthor(s): Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung
Published in: 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2019, Page(s) 5-8
DOI: 10.1109/fccm.2019.00011 - Heterogeneous Resource-Elastic Scheduling for CPU+FPGA ArchitecturesAuthor(s): Anuj Vaishnav, Khoa Dang Pham, Dirk Koch
Published in: Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies – HEART 2019, 2019, Page(s) 1-6
DOI: 10.1145/3337801.3337819 - Scalable Filtering Modules for Database Acceleration on FPGAsAuthor(s): Kristiyan Manev, Anuj Vaishnav, Charalampos Kritikakis, Dirk Koch
Published in: Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies – HEART 2019, 2019, Page(s) 1-6
DOI: 10.1145/3337801.3337810 - LLC-Guided Data Migration in Hybrid Memory SystemsAuthor(s): Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
Published in: 2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2019, Page(s) 932-942
DOI: 10.1109/ipdps.2019.00101 - End-to-end Dynamic Stream Processing on Maxeler HLS PlatformsAuthor(s): Charalampos Kritikakis, Dirk Koch
Published in: 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019, Page(s) 59-66
DOI: 10.1109/asap.2019.00-29 - BITMAN: A tool and API for FPGA bitstream manipulationsAuthor(s): Khoa Dang Pham, Edson Horta, Dirk Koch
Published in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Page(s) 894-897
DOI: 10.23919/date.2017.7927114 - Accelerating Linux Bash Commands on FPGAs Using Partial ReconfigurationAuthor(s): Edson Horta, Xinzi Shen, Khoa Pham, Dirk Koch
Published in: FPGAs for Software Programmers (FSP), 2017, 2017
Book chapters
- HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware – ECOSCALEAuthor(s): Pavlos Malakonakis, Konstantinos Georgopoulos, Aggelos Ioannou, Luciano Lavagno, Ioannis Papaefstathiou, Iakovos Mavroidis
Published in: Applied Reconfigurable Computing. Architectures, Tools, and Applications – 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings, Issue 10824, 2018, Page(s) 724-736
DOI: 10.1007/978-3-319-78890-6_58 - HLS Enabled Partially Reconfigurable Module ImplementationAuthor(s): Nicolae Bogdan Grigore, Charalampos Kritikakis, Dirk Koch
Published in: Architecture of Computing Systems – ARCS 2018, Issue 10793, 2018, Page(s) 269-282
DOI: 10.1007/978-3-319-77610-1_20 - Energy-Efficient Heterogeneous Computing at exaSCALE—ECOSCALEAuthor(s): Konstantinos Georgopoulos, Iakovos Mavroidis, Luciano Lavagno, Ioannis Papaefstathiou, Konstantin Bakanov
Published in: Hardware Accelerators in Data Centers, 2019, Page(s) 199-213
DOI: 10.1007/978-3-319-92792-3_11 - A Novel Framework for Utilising Multi-FPGAs in HPC SystemsAuthor(s): K. Georgopoulos, K. Bakanov, I. Mavroidis, I. Papaefstathiou, A. Ioannou, P. Malakonakis, K. Pham, D. Koch, L. Lavagno
Published in: Heterogeneous Computing Architectures – Challenges and Vision, 2019, Page(s) 153-189
DOI: 10.1201/9780429399602-7
- Telecommunication Systems Institute – Greece
- THE QUEEN’S UNIVERSITY OF BELFAS – United Kingdom
- STMICROELECTRONICS GRENOBLE 2 SAS – France
- ACCIONA CONSTRUCCION SA – Spain
- THE UNIVERSITY OF MANCHESTER – United Kingdom
- POLITECNICO DI TORINO – Italy
- CHALMERS TEKNISKA HOEGSKOLA AB – Sweden
- SYNELIXIS LYSEIS PLIROFORIKIS AUTOMATISMOU & TILEPIKOINONION ANONIMI ETAIRIA – Greece
- IDRYMA TECHNOLOGIAS KAI EREVNAS – Greece
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Telecommunication Systems Research Institute (T.S.I.)
Technical University of Crete
Campus – Akrotiri
73100 Chania
Greece